//`timescale 1ns / 1ps
// Company: 
// Engineer: 
// 
// Create Date: 2021/07/17 10:56:58
// Design Name: 
// Module Name: MUX_Bdata
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////



module MUX_Adata(
    input [31:0] rD1,
    input [31:0] EX_MEM_data,
    input [31:0] MEM_WB_data,
    input [1:0] Adata_sel,
    output [31:0] Adata
    );
    
    assign Adata    =   (Adata_sel==2'b01)  ?   EX_MEM_data:
                        (Adata_sel==2'b10)  ?   MEM_WB_data:
                                                rD1;
                                                
                                                
    
endmodule
